The present invention relates to integrated circuits and related multilayer structures and, more particularly, to such structures incorporating organic glass layers or other carbon-bearing elements. A major objective of the present invention is to reduce parasitic leakage in silicon based integrated circuits incorporating organic glass layers within an intermetal dielectric and a nitride layer in a passivation structure.
Much of modern technological progress is identified with the development of integrated circuits, which provide high levels of functionality in a small space and require relatively small amounts of power. These integrated circuits generally comprise a large number of devices fabricated into a substrate and electrically isolated, usually by thermally grown field oxides.
The devices, e.g., transistors, are interconnected using metal patterns formed over the substrate. Typically, at least two metallization levels and an intermetal dielectric are required so that conductive traces can cross each other without shorting. Where connections between the levels are desired, vias can be formed through the dielectric and filled with conductive material.
The metallization patterns defined in each metallization level can be defined photolithographically. The surfaces over which conductive leads are to be formed are preferably as flat as possible to maximize the precision of the photolithography. The desired flatness can be difficult to achieve beyond the first metallization layer because subsequently formed layers, e.g., oxide intermetal dielectric layers, tend to conform to the topology of the pattern in the first metallization layer and any other surface features, e.g., polycrystalline gates, formed on the substrate.
An organic glass layer can be included within an intermetal dielectric structure to provide a flatter surface upon which a subsequent metal pattern can be defined. Thus, an intermetal dielectric structure can include an organic glass layer sandwiched between two oxide layers. The organic glass can be spun on so that it tends to fill in the "valleys" in the surface below. The oxide layer above the glass is then physically buffered from the topology below the glass and thus serves as a better foundation for the photolithographic definition of the next metal pattern. The planarization process can be repeated to accommodate any third or higher level metallizations.
Once the final metallization layer is deposited and the desired pattern defined therein, it is generally desired to protect the exposed metal with a passivation structure. Passivation structures including an oxide layer followed by a nitride layer have proved effective at protecting the underlying structure from environmental attack. In accordance with the foregoing consideration, a particularly useful integrated circuit structure comprises a conventional device through a first metal level, an intermetal dielectric structure including an organic glass sandwiched between two oxide layers, a second metal level, and a passivation structure including a nitride layer over an oxide layer.
Such structures have been found to have a problem with parasitic leakage. In other words, currents applied to one device of the integrated circuit structure are unintentionally diverted to neighboring devices. Presumably, current travels under the field oxides, which are failing their objective of electrically isolating devices. Parasitic leakage impairs performance in individual integrated circuits. On a statistical basis, excessive parasitic leakage lowers yields and, correspondingly, raise manufacturing costs. From a design perspective, circuit miniaturization is limited because the parasitic leakage places a lower bound on the minimum lateral size for field oxides; smaller field oxides would increase parasitic leakage.
What is needed is, first, to identify at least some of the factors contributing to parasitic leakage. Then, an approach to minimizing parasitic leakage needs to be determined. Preferably, this approach would be compatible with conventional processing procedures and be otherwise economical.